The invention is particularly, but not exclusively, concerned with a memory device in which memory cells are formed by insulated gate transistors. These memories include EPROMS and FLASH EPROMS referred to herein as flash memories.
Flash memories having low voltage supplies of 3.3V.+-.0.3V introduce biasing problems in reading erased cells. In a large memory array the threshold voltages of erased cells (ie the gate voltage required to turn the transistor in the cell on when the source is grounded) vary over a distributed range having a maximum and a minimum. During a read operation erased cells in a memory array are required to sink current from their associated bit line when selected by turning on, whilst programmed cells are required to sink substantially no current when selected by remaining turned off.
The value of the average of the threshold voltage distribution is determined by how low the minimum can be allowed to be. If a cell is over-erased, its threshold voltage may become negative such that the cell is always turned on and sinking current from its associated bit line. In such an event all the cells associated with that same bit line will become unusable because of the over-erased cell continually sinking current, since every cell will then appear to be erased when read even if programmed. The threshold voltage distribution is therefore determined such that the minimum will never become a negative value, and in practice this results in the maximum of the threshold voltage distribution being approximately 3V.
In devices having a supply voltage of 5V.+-.10% it is ensured that applying the supply voltage via a wordline to the transistor gate of an erased cell having a threshold voltage of 3V will cause the cell to turn on and sink current. However, in devices having supply voltages of 3.3V.+-.0.3V it cannot be ensured that there will be sufficient voltage supplied to the transistor gate of an erased cell having a threshold voltage of 3V to turn such cell on to the extent that an adequate current for sensing flows. An adequate current for sensing may be 50 A, and erased cell currents are typically 100 A. In order to ensure an adequate current for sensing it is necessary to supply a voltage via the wordline to the transistor gate of an erased cell of at least 4V when the threshold voltage of such a cell is approximately 3V. Therefore when using a memory device having a low voltage supply, some means of raising the supply voltage applied to the wordline during a read operation is required.
It is unnecessary, during a read operation, to raise the supply voltage applied to the wordline to a level such that a programmed cell is turned on. Programmed cells generally do not switch on during read operations because the threshold voltages of their associated transistors is high, typically greater than 5V.
There are two commonly known ways for raising the voltage on the wordline above the supply voltage Vcc. The first known method is a charge pump which comprises a circuit with several stages, each stage providing a charge transfer using a clock, a diode and a capacitor to raise the potential of its stage outputs. Each stage raises the potential above the output of the previous stage so that the difference between the actual supply voltage of the device and the output of the charge pump can be several volts. Such a scheme provides a constantly high level for the wordline supply.
The second known method is the single-shot boost scheme. In such a scheme the voltage supply is boosted using a single capacitor to transfer an amount of charge sufficient to provide the required voltage to the wordline. With this scheme the wordline voltage need only be raised until the sensing operation is complete. After sensing, the signal level of the wordline can be returned to the level of the supply.
When used in an asynchronous environment, both schemes have particular design requirements. The charge-pump scheme requires a clock that runs continuously to keep the output of the charge pump at the required voltage level. The output of the charge pump will have a voltage ripple due to leakage and therefore the value of the output of the charge pump cannot be accurately defined. In addition, when many addresses are continually changing in an asynchronous environment it is possible that the output level of the charge pump may be `walked down`, ie fall in response to each change in address. Furthermore the requirement for the clock to continually run consumes a considerable amount of power, which is a severe restraint in applications where an extremely low power requirement is essential, for example in laptop computer applications and especially in standby mode.
With the single shot boost scheme it is important to have a well defined level on the wordline during the time that the cell is accessed. In the case of asynchronous operation, where the addresses may transition at any time, it is desirable to boost the supply above the supply voltage only once the addresses have become stable. The single shot boost scheme does not suffer from the above power consumption problems since the supply need only be boosted when needed by being triggered by an address transistion detection pulse and is in a quiescent state when the chip is disabled.